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h anb it hdd128m72d18rpw url : www.hbe.co.kr 1 hanbit electronics co.,ltd. rev 1.0 (january. 2005) general description th e hdd128m72d18rpw is a 128 m x 72 bit double data rate(ddr) synchronous dynamic ram high - density memory module. the module consists of eighteen cmos 64 m x 8 bit with 4banks ddr sdram s in 66pin tsop - ii 400mil package s and 2k eeprom in 8 - pin tssop package on a 184 - pin glass - epoxy. four 0. 1 uf decoupling capacitors are mounted on the printed circuit board in parallel for each ddr sdram. the hdd128m72d18rpw is a di mm ( dual in line memory module ) . synchronous design allows precise cycle c ontrol with the use of system clock. data i/o transactions are possible on both edges of dqs . range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance mem ory system applications . a ll module components may be powered from a single 2.5 v dc power supply and all inputs and outputs are sstl_2 compatible. features ? p art identification hdd128m72d18rpw C 13a : 1 33 mhz (cl= 2 ) hdd128m72d18rp w C 13b : 1 33 mhz (cl= 2.5 ) hdd128m72d18rpw C 16b : 1 66 mhz (cl= 2.5 ) ? 1024mb(64mx72) register ed ddr dimm based on 64mx8 ddr sdram ? 2.5v 0.2v vdd and vddq power supply ? auto & self refresh capability ( 8k cycles / 64ms) ? all input and output are comp atible with sstl_2 interface ? data(dq), data strobes and write masks latched on the rising and falling edge s of the clock ? all addresses and control inputs except data(dq), data strobes and data masks latched on the rising edge s of the clock ? mrs cycle with address key programs - latency (access from column address) : 2, 2.5 - burst length : 2, 4, 8 - data scramble : sequential & interleave ? data(dq), data strobes and write masks latched on the rising and falling edge s of the clock ? all addresses and control inputs except data(dq), data strobes and data masks latched on the rising edge s of the clock ? the used device is 16m x 8bit x 4banks ddr sdram ddr sdram module 1024mbyte (128mx72bit), based on 64mx8, 4banks, 8k ref., 184pin - dimm with pll & register part no . h dd128m72d18rpw
h anb it hdd128m72d18rpw url : www.hbe.co.kr 2 hanbit electronics co.,ltd. rev 1.0 (january. 2005) pin assignment * : these pins are not used in this module. pin pin descr iption pin pin description a0~a12 address input vdd power supply(2.5v) ba0~ba1 bank select address vddq power supply for dqs(2.5v) dq0~dq63 data input/output vref power supply for reference cb0~cb7 check bit vddspd serial eeprom power supply(3.3) dqs0 ~dqs8 data strobe input/output vss ground dm0~dm8 data - in mask sa0~sa2 address in eeprom ck0~/ck0 clock input sda serial data i/o cke0~cke1 clock enable input scl serial clock /cs0~/cs1 chip select input vddid vdd identification flag /ras row address strobe nc no connection /cas column address strobe pin front pin back pin frontl pin back pin front pin back 1 vref 32 a5 62 v ddq 93 v ss 124 v ss 154 /ras 2 dq0 33 dq24 63 /we 94 dq4 125 a6 155 dq45 3 v ss 34 v ss 64 dq41 95 dq5 126 dq28 156 v ddq 4 dq1 35 dq25 65 /cas 96 v ddq 127 dq29 157 /cs0 5 dqs0 36 dqs3 66 v ss 97 dm0 128 v ddq 158 /cs1 6 dq2 37 a4 67 dqs5 98 dq6 129 dm3 159 dm5 7 v dd 38 v dd 68 dq42 99 dq7 130 a3 160 v ss 8 dq3 39 dq26 69 dq43 100 v ss 131 dq30 161 dq46 9 nc 40 dq27 70 v dd 101 nc 132 v ss 162 dq47 10 /reset 41 a2 71 * /cs2 102 nc 133 dq31 163 * /cs3 11 v ss 42 v ss 72 dq48 103 *a13 134 cb4 164 v ddq 12 dq8 43 a1 73 dq49 104 v ddq 135 cb5 165 dq52 13 dq9 44 cb0 74 v ss 105 dq12 136 v ddq 166 dq53 14 dqs1 45 cb1 75 * ck2 106 dq13 137 ck0 167 nc 15 v ddq 46 v dd 76 * /ck2 107 dm1 138 /ck0 168 v dd 16 * ck1 47 dqs8 77 v ddq 108 v dd 139 v ss 169 dm6 17 * /ck1 48 a0 78 dqs6 109 dq14 140 dm8 170 dq54 18 v ss 49 cb2 79 dq50 110 dq15 141 a10 171 dq55 19 dq10 50 v ss 80 dq51 111 cke1 142 cb6 172 v ddq 20 dq11 51 cb3 81 v ss 112 v ddq 143 v ddq 173 nc 21 cke0 52 ba1 82 vddid 113 * ba2 144 cb7 174 dq60 22 v ddq key 83 dq56 114 dq20 k ey 175 dq61 23 dq16 53 dq32 84 dq57 115 a12 145 v ss 176 v ss 24 dq17 54 v ddq 85 v dd 116 v ss 146 dq36 177 dm7 25 dqs2 55 dq33 86 dqs7 117 dq21 147 dq37 178 dq62 26 v ss 56 dqs4 87 dq58 118 a11 148 v dd 179 dq63 27 a9 57 dq34 88 dq59 119 dm2 149 dm4 180 v d dq 28 dq18 58 v ss 89 v ss 120 v dd 150 dq38 181 sa0 29 a7 59 ba0 90 nc 121 dq22 151 dq39 182 sa1 30 v ddq 60 dq35 91 sda 122 a8 152 v ss 183 sa2 31 dq19 61 dq40 92 scl 123 dq23 153 dq44 184 vddspd
h anb it hdd128m72d18rpw url : www.hbe.co.kr 3 hanbit electronics co.,ltd. rev 1.0 (january. 2005) f unctional block diagram a0 - a12
h anb it hdd128m72d18rpw url : www.hbe.co.kr 4 hanbit electronics co.,ltd. rev 1.0 (january. 2005) pin function description pin name input function ck, / ck clock ck and / ck are differential clock inputs. all address and control input signals are sampled on the positive edge of ck and negative edge of / ck. output (read) data is referenced to both edges of ck. internal clock signals are derived from ck/ / ck. cke clock enable cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. deactivating the clock provides precharge power - down and self refresh operation (all banks idle), or active power - down(row active in any bank). cke is synchronous for all functions except for disabling outputs, which is achieved asynchronously. input buffers, excluding ck, ck and cke are disabled during power - down and self refresh modes, providing low standby power. cke will recognizean lvcmos low level prior to vref being stable on power - up. /cs0, /cs1 chip select cs enables(re gistered low) and disables(registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. a0 ~ a1 2 address row/co lumn addresses are multiplexed on the same pins. row address : ra0 ~ ra1 2 , column address : ca0 ~ ca 9, ca11 ba0 ~ ba1 bank select address b a0 and ba1 define to which bank an active, read, write or pre - charge command is being applied. / ras row address str obe latches row addresses on the positive going edge of the clk with / ras low. enables row access & precharge. / cas column address strobe latches column addresses on the positive going edge of the clk with / cas low. enables column access. / we write enabl e enables write operation and row precharge. latches data in starting from / cas, / we active. dq s 0 ~ 7 data strobe output with read data, input with write data. edge - aligned with read data, cen - tered in write data. used to capture write data. dm0~7 inpu t data mask dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. dm pins include dummy loading internally, to matches the dq and dqs lo ad - ing. dq0 ~ 63 data input/output data inputs/outputs are multiplexed on the same pins. vddq supply dq power supply : +2.5v 0.2v. vdd supply power supply : +2.5v 0.2v (device specific). vss supply dq ground. vref supply sstl_2 reference voltage. vspd supply serial eeprom power supply : 3.3v vddid vdd identification flag
h anb it hdd128m72d18rpw url : www.hbe.co.kr 5 hanbit electronics co.,ltd. rev 1.0 (january. 2005) absolute maximum ratings parameter symbol rating unte voltage on any pin relative to vss v in , v out - 0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd - 1.0 ~ 3.6 v vol tage on v ddq supply relative to vss v ddq - 0.5 ~ 3.6 v storage temperature t stg - 55 ~ +150 c power dissipation p d 1.5 * # of component w short circuit current i os 50 ma notes: operation at above absolute maximum rating can adversely affect device relia bility dc operating con ditions ( recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) ) parameter symbol min max unit note supply voltage v dd 2.3 2.7 v i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref 0.49*vd dq 0.51* vddq v 1 i/o termination voltage (system) v tt v ref C 0.04 v ref + 0.04 v 2 input high voltage v ih (dc) v ref + 0.15 v ref + 0.3 v input low voltage v il (dc) - 0.3 v ref - 0.15 v input voltage level, ck and /ck inputs v in (dc) - 0.3 v ddq + 0.3 v in put differential voltage , ck and /ck inputs v id (dc) 0.3 v ddq + 0.6 v input leakage current i l i - 2 2 ua 3 out put leakage current i oz - 5 5 ua out put high current (normal strength driver) ; v out =v tt + 0.84v i oh - 16.8 ma out put low current (normal strength driver) ; v out =v tt - 0.84v i o l 16.8 ma out put high current (half strength driver) ; v out =v tt + 0.45v i oh - 9 ma notes : 1. includes 25mv margin for dc offset on v re f , and a combined total of 50mv margin for all ac noise and dc offset on v re f , bandwidth limited to 20mhz. the dram must accommodate dram current spikes on v ref and internal dram noise coupled to v re f , both of which may result in v ref noise. v ref should be de - coupled with an inductance of 3nh. 2.v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v re f , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on / ck. 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specifications are relative to a v ref envelop that has been bandwidth limited to 200mhz.
h anb it hdd128m72d18rpw url : www.hbe.co.kr 6 hanbit electronics co.,ltd. rev 1.0 (january. 2005) input / outpu t capacitance ( v dd = min to max, v ddq = 2.5v to 2.7v, t a = 2 5 c, f = 1 00 mhz) description symbol min max units input capacitance(a0~a12, ba0~ba1, / ras, / cas ,/we) c in1 9 11 pf input capacitance(cke0,cke1) c in2 9 11 pf input capacitance(/cs0) c in3 9 11 p f input capacitance(ck0~ck2, /ck0~/ck2) c in4 11 12 pf input capacitance(dm0~dm7) c in5 14 16 pf d ata input/output capacitance (dq0 ~ dq 63, dqs0~dqs7 ) c out1 14 16 pf d ata input/output capacitance ( cb0~cb7) c out2 14 16 pf d c characteristics (v dd = 2.7 v, t = 10 c ) symbol - 16b (ddr333@cl=2.5) - 13a (ddr266@cl=2.0) - 13b (ddr266@cl=2.5) unit notes idd0 2230 2010 2010 ma idd1 2500 2280 2280 ma idd2p 590 540 540 ma idd2f 1420 1290 1290 ma idd2q 950 900 900 ma idd3p 1040 990 990 ma idd3n 1690 1560 1560 ma idd4r 2540 2280 2280 ma idd4w 2630 2330 2330 ma idd5 3130 2910 2910 ma normal 590 540 540 ma idd6 low power 560 510 510 ma optional idd7a 4520 4080 4080 ma notes: module idd was calculated on the basis of component idd and can be dif ferently measured according to dq loading cap. ac operating conditions parameter s tmbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih (ac) vref + 0.35 input low (logic 0) voltage, dq, dqs and dm signals. v il (ac) vref - 0.3 1 v input differential voltage, ck and ck inputs v id (ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs v ix (ac) 0.5*vddq - 0.2 0.5*vddq+0.2 v 2 notes: 1. vid is the magnitude of the difference between the input level on ck and t he input on / ck. the value of v ix is expected to equal 0.5* v ddq of the transmitting device and must track variations in the dc level of the s ame 3. these parameters should be tested at the pim on actual components and may be checked at either the pin or t he pad in simula - tion. the ac and dc input specificatims are refation to a vref envelope that has been bandwidth limited 20mhz.
h anb it hdd128m72d18rpw url : www.hbe.co.kr 7 hanbit electronics co.,ltd. rev 1.0 (january. 2005) ac c haracteristics (these ac char a cteristics were test ed on the component) ddr333@cl=2.5 ddr266a@cl=2.0 dd r266b@cl=2.5 - 16b - 13a - 13b parameter symbol min max min max min max unit note row cycle time t rc 60 65 65 ns refresh row cycle time t rfc 72 75 75 ns row active time t ras 42 70k 45 120k 45 120k ns / ras to / cas delay t rcd 18 20 20 ns row precharg e time t rp 18 20 20 ns row active to row active delay t rrd 12 15 15 ns write recovery time t wr 15 15 15 t ck last data in to read command t wt r 1 1 1 t ck col. address to col. address delay t ccd 1 1 1 t ck cl=2.0 7 .5 12 7.5 12 10 12 ns clock cycle time cl=2.5 t ck 6 12 7.5 12 7.5 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs - out access time from ck/ck t dqsck - 0.6 +0.6 - 0.75 +0.75 - 0.75 +0.75 ns output data access time from ck/ck t ac - 0.7 +0.7 - 0.75 +0.75 - 0.75 +0.75 ns data strobe edge to ouput data edge t dqsq - 0.45 - +0.5 - +0.5 ns 12 read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck ck t o valid dqs - in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs - in setup time t wpres 0 0 0 ns 3 dqs - in hold time t wpreh 0.25 0.25 0.25 t ck dqs - in falling edge to ck rising - setup time t d ss 0.2 0.2 0.2 t ck dqs - in falling edge to ck rising hold tim e t dsh 0.2 0.2 0.2 t ck dqs - in high level width t dqsh 0.35 0.35 0.35 t ck dqs - in low level width t dqsl 0.35 0.35 0.35 t ck dqs - in cycle time t dsc 0.9 0.9 1.1 0.9 1.1 t ck address and control input setup time (fast) t is 0.75 0.9 0.9 ns i, 5.7 ~9 address and control input hold time (fast) t ih 0.75 0.9 0.9 ns i, 5.7~9 address and control input setup time (slow) t is 0.8 1.0 1.0 ns i, 6~9
h anb it hdd128m72d18rpw url : www.hbe.co.kr 8 hanbit electronics co.,ltd. rev 1.0 (january. 2005) address and control input hold time (slow) t ih 0.8 1.0 1.0 ns i, 6~9 data - out high impedence time from ck/ck t hz - 0.7 +0.7 - 0.75 +0.75 - 0.75 +0.75 ns 1 data - out low impedence time from ck/ck t lz - 0.7 +0.7 - 0.75 +0.75 - 0.75 +0.75 ns 1 input slew rate(for input only pins) t sl(io) 0.5 0.5 0.5 ns input slew rate(for i/o pins) t sl(o) 0.5 0.5 0.5 t c k output slew rate(x4,x8) t sl(o) 1.0 4.5 1.0 4.5 1.0 4.5 t ck output slew rate(x16) t sl(o) 0.7 5 0.7 5 0.7 5 output slew rate matching ratio(rise to fall) t slmr 0.67 1.5 0.67 1.5 0.67 1.5 mode register set cycle time t mrd 12 15 15 ns d q & dm setup time to dqs t ds 0.45 0.5 0.5 ns j, k dq & dm hold time to dqs t dh 0.45 0.5 0.5 ns j, k control & address input pulse width t ipw 2.2 2.2 2.2 ns 8 dq & dm input pulse width t dipw 1.75 1.75 1.75 ns 8 power down exit time t pdex 6 7.5 7.5 ns exit self refresh to non - read command t xsnr 75 75 75 ns exit self refresh to read command t xsrd 200 200 200 t ck refresh interval time t refi 7.8 7.8 7.8 ns 4 output dqs valid window t qh t hp - t qhs - t hp - t qhs - t hp - t qhs - ns 11 clock half period t hp t clmin or t chmin - t clmin or t chmin - t clmin or t chmin - ns 10,11 data hold skew factor t qhs 0.55 0.75 0.75 ns 11 dqs write postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 2 active to read with auto precharge command t rap 1 8 20 20 autoprecharge write recovery + precharge time t dal (t wr /t ck )+ (t rp /t ck ) (t wr /t ck )+ (t rp /t ck ) (t wr /t ck )+ (t rp /t ck ) t ck 13 notes : maximum burst refresh of 8. t hzq transitions occurs in the same assess time windows as valid data transiti ons. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving. the specific requirement is that dqs be valid (high - low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on t dqss . the maximum limit for this parameter is not a device limit. the device will operate with a great v alue for this parameter, but system performance (bus turnaround) will degrade accordingly.
h anb it hdd128m72d18rpw url : www.hbe.co.kr 9 hanbit electronics co.,ltd. rev 1.0 (january. 2005) system characteristics for ddr sdram the following specification parameters are required in systems using ddr333, ddr266 devices to ensure proper system p erformance. these characteristics are for system simulation purposes and are guaranteed by design. table 1 : input slew rate for dq, dqs, and dm ac characteristics ddr333 ddr266 parameter symbol min max min max units notes dq/dm/dqs input slew rate m easured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew tbd tbd tbd tbd v/ns a, m table 2 : input setup & hold time derating for slew rate input slew rate tis tih units notes 0.5 v/ns 0 0 ps i 0.4 v/ns +50 0 ps i 0.3 v/ns +100 0 ps i table 3 : input/output setup & hold time derating for slew rate input slew rate tds tdh units notes 0.5 v/ns 0 0 ps k 0.4 v/ns +75 +75 ps k 0.3 v/ns +150 +150 ps k table 4 : input/output setup & hold derating for rise/fall delta slew rate delta slew rate tds tdh units notes +/ - 0.0 v/ns 0 0 ps j +/ - 0.25 v/ns +50 +50 ps j +/ - 0.5 v/ns +100 +100 ps j table 5 : output slew rate characteristice (x4, x8 devices only) slew rate characteri stic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullu p slew rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h table 6 : output slew rate characteristice (x16 devices only) slew rate characteri stic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h table 7 : output slew rate matching ratio characteristics ac characteristics ddr333 ddr266 parameter min max min max notes output slew rate matching ratio (pullup to pulldown) tbd tbd tbd tbd e,m
h anb it hdd128m72d18rpw url : www.hbe.co.kr 10 hanbit electronics co.,ltd. rev 1.0 (january. 2005) component notes 1. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (hz), or begins driving (lz). 2. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 3. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the b us, dqs will be tran sitioning from high - z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 4. a maximum of eight auto refresh commands can be posted to any giv en ddr sdram device. 5. for command/address input slew rate 1.0 v/ns 6. for command/address input slew rate 0.5 v/ns and < 1.0 v/ns 7. for ck & ck slew rate 1.0 v/ns 8. these parameters guarantee device timing, but they are not necessarily tested on each device. they may be guaranteed by device design or tester correlation. 9. slew rate is measured between voh(ac) and vol(ac). 10. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tcl and tch).....for example, tcl and tch are = 50% of the period, less the half period jitter (tjit(hp)) of the clock source, and less the half period jitter due to crosstalk (tjit(crosstalk)) into the clock traces. 11. tqh = thp - tqhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs accounts for 1) the pulse duration distortion of on - chip clock circuits; and 2) the worst case push - out of dqs on one tansition followed by the worst case pull - in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and pchannel to n - channel variation of the output driver s. 12. tdqsq consists of data pin skew and output pattern effects, and p - channel to n - channel variation of the output drivers for any given cycle. 13. tdal = (twr/tck) + (trp/tck) for each of the terms above, if not already an integer, round to the next highest integer. example: for ddr266b at cl=2.5 and tck=7.5ns tdal = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tdal = 5 clocks
h anb it hdd128m72d18rpw url : www.hbe.co.kr 11 hanbit electronics co.,ltd. rev 1.0 (january. 2005) system notes : a. pullup slew rate is characteristized under the test conditions as shown in figure 1. b. pulldown slew rate is measured under the test conditions shown in figure 2. c. pullup slew rate is measured between (vddq/2 - 320 mv +/ - 250 mv) pulldown slew rate is measured between (vddq/2 + 320 mv +/ - 250 mv) pullup and pulldown slew rate conditio ns are to be met for any pattern of data, including all outputs switching and only one output switching. example : for typical slew rate, dq0 is switching for minmum slew rate, all dq bits are switching from either high to low, or low to hi gh. the remaining dq bits remain the same as for previous state. d. evaluation conditions typical : 25 c (t ambient), vddq = 2.5v, typical process minimum : 70 c (t ambient), vddq = 2.3v, slow - slow process maximum : 0 c (t ambient), vddq = 2.7v, fast - fast process e. the ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. for a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. verified under typical conditions for qualification purposes. g. tsopii package divices only. h. only intended for operation up to 266 mbps per pin. i. a derating factor will be used to increase tis and tih in the case where the input slew rate is below 0.5v/ns as shown in table 2. the input slew rate is based on the lesser of the slew rates detemined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. j. a derating factor will be used to increase tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in tables 3 & 4. input slew rate is based on the larger of ac - ac delta rise, fall rate and dc - dc delta rise, input slew rate is based on the lesser of the slew rate s determined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. the delta rise/fall rate is calculated as: {1/(slew rate1)} - {1/(slew rate2)} for example : if slew rate 1 is 0.5 v/ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is - 0.5ns/v . using the table given, this would result in the need for an increase in tds and tdh of 100 ps. k. table 3 is used to increase tds and tdh in the case where the i/o slew rate is below 0.5 v/ns. the i/o slew rate is bas ed on the lesser on the lesser of the ac - ac slew rate and the dc - dc slew rate. the inut slew rate is based on the lesser of the slew rates deter mined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), and similarly for rising transitions. m. dqs, dm, and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotony.
h anb it hdd128m72d18rpw url : www.hbe.co.kr 12 hanbit electronics co.,ltd. rev 1.0 (january. 2005) simplified truth table command cke n - 1 cke n /cs /r a s /c a s /we dm ba 0,1 a10/ ap a11,a12 a9~a0 note register extended mrs h x l l l l x op code 1,2 register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh self refresh exit l h h x x x x x 3 bank active & ro w addr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge e able h x l h l h x v h column address 4 auto precharge disable h l 4 write & column address auto precharge en a ble h x l h l l x v h column address 4,6 burst stop h x l h h l x x 7 bank selection v l precharge all banks h x l l h l x x h x 5 h x x x entry h l l v v v x clock suspend or active power down exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down mode exit l h l v v v x x dm h x v x 8 h x x x no operation command h x l h h h x x (v=valid, x=don't care, h=logic high, l=logic low) notes : 1. op code : operand code a0 ~ a1 1 & ba0 ~ ba 1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatic al precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba0 ~ ba 1 : bank select addresses. if both ba0 and ba1 are "low" at read, write, row active and precharge, bank a is selec ted. if both ba0 is "low" and ba1 is "high" at read, write, row active and precharge, bank b is selected. if both ba0 is "high" and ba1 is "low" at read, write, row active and precharge, bank c is selected. if both ba0 and ba1 are "high" at read, write, ro w active and precharge, bank d is selected. if a10/ap is "high" at row precharge, ba0 and ba1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write comma nd can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. dm sampled at the rising and falling edges of the dqs and data - in are masked at the both edges ( write dm latency is 0 )
h anb it hdd128m72d18rpw url : www.hbe.co.kr 13 hanbit electronics co.,ltd. rev 1.0 (january. 2005) p ackaging information unit : mm < rear C side > *** pcb thickness : 1.27 0.08 mm 30.48 0.20 133.35 0.20 a b 133.35 0.20 30.48 0.20
h anb it hdd128m72d18rpw url : www.hbe.co.kr 14 hanbit electronics co.,ltd. rev 1.0 (january. 2005) o r dering information part number density org. package ref. vcc mode max.frq hdd128m72d18 rpw - 16b 1024mbyte 128m x 72 184pin dimm 8k 2.5v ddr registered 166mhz/cl2 ddr333 hdd128m72d18rpw - 13a 1024mbyte 128m x 72 184pin dimm 8k 2.5v ddr registered 133mhz/cl2 ddr266 hdd128m72d18rpw - 13b 1024mbyte 128m x 72 184pin dimm 8k 2.5v ddr registered 133mh z/cl2.5 ddr266

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